Field of the Invention
The invention relates to a redundancy concept for integrated memory circuits having ROM memory cells.
Hardware redundancy in integrated memories is generally understood to be address replacement of addressable units of memory cells within the memory by redundant units of memory cells. In this case, the addressable units may be word or bit lines, for example. The so-called situation of redundancy occurs when it is established during a memory test that one of the replaceable addressable units has defects. The memory is then manipulated such that upon application of the address of the unit to be replaced, the redundant unit rather than the latter is addressed. In general, a corresponding memory test is carried out following fabrication of the memory, with the result that the redundancy repair can be performed immediately afterward.
In the case of RAM memories (Random Access Memory, read and write memory), it is customary to provide redundant word or bit lines which likewise have RAM memory cells, like the "normal" word and bit lines.
One possible way of providing redundancy in a ROM memory (Read Only Memory) is described in U.S. Pat. No. 5,388,075, which shows that defective ROM memory cells are replaced by redundant programmable ROM memory cells (PROM memory cells). The ROMs which, in the event of redundancy, are programmed by fuses in such a way that they subsequently contain the data to be stored in the memory cells to be replaced. The solution has the disadvantage that the redundant memory cells, in the form of PROM memory cells, are relatively large.
U.S. Pat. No. 4,601,031 describes a repairable ROM memory in which a defective row of ROM memory cells is replaced by a redundant row having RAM memory cells. Each column of the ROM memory cell array contains a check bit, and the data to be stored in the redundant row are reconstructed with the aid of the check bit. Reconstructed data are written to the redundant row in the course of initialization of the memory.